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2-channel, 10 v input range, high throughput, 24-bit -? adc ad7732 features high reso lutio n adc 24 bits no miss ing codes 0.001 5% nonlinearity optimized for f a st channel swi t ching 18-bit p-p resolution (21 bits effectiv e) at 500 hz 16-bit p-p resolution (19 bits effectiv e) at 2 khz 14-bit p-p resolution (18 bits effectiv e) at 15 khz on-chip per ch annel syst em c a libration 2 ful l y differ e ntial analog inp u ts input ranges + 5 v, 5 v, +1 0 v, 1 0 v overvoltage to lerant up to 16.5 v not affecting adj a cent channel up to 50 v ab solute maximum 3-wire seri al in terface spi?, qspi?, m i crowire?, and dsp compatible schmitt trigger on logic inputs single-supply operation 5 v an alog sup p ly 3 v o r 5 v digit a l supply package: 28- le ad tssop applic ati o ns plcs/dcs multiplexing a pplications process control industrial instr u mentation general description the ad7732 is a hig h p r ecisio n, hig h thr o ug h p u t a n alog f r o n t e n d . t r ue 16- b i t p- p r e so l u ti o n is a c h i eva b l e w i t h a t o tal co n v ersio n t i m e o f 500 s (2 kh z c h a n ne l s w i t chin g), making i t ide a l l y sui t ab le fo r hig h r e s o l u t i o n m u l t i p lexin g a p plic a t io ns. the p a r t ca n b e co nf igur e d v i a a sim p le dig i t a l in ter f ace, w h ich al lo ws us ers t o b a lan c e t h e n o is e p e r f o r ma n c e aga i n s t da t a t h r o ug h p u t u p to a 15.4 khz. the a n alog f r o n t end fe a t ur es t w o f u l l y dif f er e n t i al in p u t ch an nel s w i t h u n i p ol ar or t r u e b i p o l a r i n put r a nge s to 1 0 v wh ile o p e r a t in g f r o m a si n g le +5 v a n alog s u p p l y . t h e pa r t h a s a n o v er r a n g e a nd under r a n ge d e te c t io n ca p a b i l i ty and accepts an an a l o g i n put ove r volt age to 1 6 . 5 v w i t h out d e g r a d i n g t h e p e r f or m a nc e of t h e a d j a c e n t ch a n n e l s . func tio n a l block di agram p0 sync/p1 ain0(+) ain1(+) ain0(? ) ain1(? ) sclk din dout cs reset rdy dgnd mclkin mclkout agnd av dd dv dd buffer reference detect refin( ? ) refin(+) ad7732 24-bit ?? adc serial interface control logic clock generator calibration circuitry i/o port mux fi g u r e 1 . the dif f er en t i al r e fer e n c e i n p u t fe a t ur es n o- re fer e n c e de t e c t ca p a b i li ty . th e ad c a l s o su pp o r ts p e r cha nnel syst em ca lib r a t ion o p t i o n s. t h e dig i t a l s e r i a l in ter f ace ca n b e co nf igur e d fo r 3-w i r e o p er a t io n a nd is com p a t i b le wi t h micr o c o n tr ol lers a nd dig i tal sig n al p r o c es s o rs. al l in t e r f ace in p u ts a r e s c h m i t t t r ig ger e d . the p a r t is s p e c if ie d fo r o p era t i o n o v er t h e ext e n d e d i n d u s t r i al t e m p era t ur e ra ng e o f C40c t o +105c. o t h e r p a r t s in t h e ad7732 famil y a r e th e ad7 734 a nd th e ad7738. the ad7734 is simila r t o ad77 32, b u t i t s a n alog f r o n t end fe a t u r e s fou r s i ng l e - e nd e d i n put ch an nel s . the ad7738 a n alog f r o n t en d is co nf igura b le f o r f o ur f u ll y dif f er en t i al o r ei g h t sin g le -e n d e d in p u t chann e l s , fe a t ur es 0.625 v t o 2.5 v b i p o la r/uni p ol ar in p u t ra n g es, a nd accep t s a co mm o n -mo d e in p u t v o l t a g e f r o m 200 mv t o a v d d C 300 mv . the ad7738 m u l t i p lexer o u t p u t is p i nn e d o u t ext e r n al l y , al lo win g t h e us e r t o im ple m en t p r og ra mma b l e ga in o r sig n al co ndi t i onin g b e fo r e b e in g a p pli e d to t h e ad c. rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed .
ad7732 table of conte n ts ad7732s p ecif ica t io n s .................................................................. 3 t i min g s p e c if ic a t io n s ....................................................................... 6 a b s o l u t e m a xim u m r a t i n g s ............................................................ 8 t y p i cal p e r f o r ma n c e c h a r ac t e r i s t ics ............................................. 9 o u t p u t n o is e and res o l u t i o n s p e c if ic a t io n ................................ 10 c h o p pin g enable d ...................................................................... 10 c h o p pin g dis a b l e d ..................................................................... 11 p i n c o nf igura t io n s an d f u n c t i onal d e s c r i p t io ns ...................... 12 reg i st er d e s c r i p t io n ....................................................................... 14 reg i st er a cce s s ............................................................................ 15 c o mm unica t ion s r e g i s t er ......................................................... 15 i/o p o r t r e g i s t e r ......................................................................... 16 r e vision r e g i s t er ........................................................................ 16 t e st r e g i s t er ................................................................................ 16 ad c s t a t us re g i s t er ................................................................... 17 c h e c ks u m r e g i s t er ..................................................................... 17 ad c z e r o -s cal e c a li b r a t ion r e g i s t er ..................................... 17 ad c f u l l -s cale reg i st er ............................................................ 17 c h a n n e l d a t a r e g i s t ers ............................................................. 17 c h a n n e l z e r o -s cale c a lib r a t ion reg i st ers .............................. 18 c h a n n e l f u l l -s c a le c a li b r a t ion reg i st ers ................................ 18 c h a n n e l s t a t us reg i st ers ........................................................... 18 c h a n n e l s e t u p reg i st ers ............................................................ 19 c h a n n e l c o n v e r sio n t i m e reg i s t ers ....................................... 19 m o de r e g i s t er ............................................................................. 20 dig i t a l i n ter f ace d e s c r i p t ion . ....................................................... 22 h a r d wa r e ..................................................................................... 22 res e t ............................................................................................. 23 a cces s t h e ad7 732 reg i st ers . ................................................... 23 s i n g le c o n v ersio n an d re adin g d a t a ...................................... 23 d u m p m o de ................................................................................ 24 c o n t in uo us c o n v ersio n m o de ................................................. 24 c o n t in uo us re ad (c o n t i n u o u s c o n v ersio n ) m o de .............. 25 cir c ui t d e s c r i p t io n ......................................................................... 26 analog f r o n t end ....................................................................... 26 analog i n p u t s e x t e n d e d v o l t ag e r a n g e ................................. 27 c h o p pin g ..................................................................................... 27 m u l t i p lexer , c o n v ersio n , and d a t a o u t p u t t i min g .............. 28 s i g m a-d e l t a a d c ....................................................................... 28 f r e q uen c y re s p o n s e .................................................................. 29 v o l t a g e refer e nce i n pu ts ........................................................... 29 refer e nce d e t e c t ......................................................................... 29 i/o p o r t ........................................................................................ 30 c a li b r a t io n ................................................................................... 30 ad c z e r o -s cal e s e lf-c al i b r a t i on ............................................ 30 p e r c h a n n e l s y s t em c a l i b r a t io n . ............................................. 30 h i g h c o mm o n -m o d e v o l t a g e a p plica t ion . ............................ 31 o u t l in e dim e n s io n s ....................................................................... 32 revision history rev i s i o n 0: i n i t ial v e r s i o n rev. 0 | page 2 of 3 2
ad7732 rev. 0 | page 3 of 3 2 ad7732?specifications table 1. (?40c to +105c; av dd = 5 v 5%; dv dd = 2.7 v to 3.6 v, or 5 v 5%; bias (all), re fin(+) = 2.5 v; refin(?) = agnd; ra, rb, rc, rd op en circuit; ain range = 10 v; f mclkin = 6.144 mhz; unless otherwise noted.) parameter min typ max unit test conditions/comments adc performance chopping enabled conversion time rate 372 12190 hz configure via conv. time register no missing codes 1, 2 24 bits fw 6 (conversion time 165 s) output noise see table 4 resolution see table 5 and table 6 integral nonlinearity (inl) 1, 2, 3 0.0003 0.0015 % of fsr f mclkin = 2.5 mhz, v cm = 0 v integral nonlinearity (inl) 2, 3 0.0010 0.0030 % of fsr f mclkin = 6.144 mhz, v cm = 0 v offset error (unipolar, bipolar) 4 10 mv before calibration offset drift vs. temperature 1 2.5 v/c gain error 3 0.7 % before calibration gain drift vs. temperature 1 3.2 ppm of fs/c positive full-scale error 4 0.7 % of fsr before calibration positive full-scale drift vs. temp. 1 3 ppm of fs/c bipolar negative full-scale error 5 0.0060 % of fsr after calibration common-mode rejection 50 65 db at dc power supply sensitivity 4 10 lsb 16 at dc, ain = 7 v, av dd = 5 v 5% channel-to-channel isolation 100 db at dc, maximum 16.5 v ain voltage adc performance chopping disabled conversion time rate 737 15437 hz configure via conv. time register no missing codes 1, 2 24 bits fw 8 (conversion time 117 s) output noise see table 7 resolution see table 8 and table 9 integral nonlinearity (inl) 2, 3 0.0015 % of fsr offset error (unipolar, bipolar) 6 10 mv before calibration offset drift vs. temperature 25 v/c gain error 4 0.5 % before calibration gain drift vs. temperature 5.3 ppm of fs/c positive full-scale error 4 0.5 % of fsr before calibration positive full-scale drift vs. temp. 4 ppm of fs/c bipolar negative full-scale error 5 0.0060 % of fsr after calibration common-mode rejection 55 db at dc power supply sensitivity 4 lsb 16 at dc, ain = 7 v, av dd = 5 v 5% channel-to-channel isolation 100 db at dc, maximum 16.5 v ain voltage analog inputs analog input differential voltage 7 10 v range r 10 v 0 v to +10 v range 0 to +10 v 5 v range r 5 v 0 v to +5 v range 0 to +5 v ain absolute voltage 1, 2, 8 ?16.5 +16.5 v bias voltage 1 0 2.5 av dd v ra, rb, rc, rd voltage 1 ?10.5 +20 v ain impedance 1, 9 100 124 k ain pin impedance 1, 9 87.5 108.5 k
ad7732 p a r a m e t e r m i n t y p m a x u n i t t e s t condition s / c o m m e n t s bias pin impedance 1, 9 1 2 . 5 1 5 . 5 k ? ?
ad7732 rev. 0 | page 5 of 3 2 parameter min typ max unit test condition s /comments dv dd current (normal mode) 14 1.0 1.5 ma dv dd = 3 v power dissipation (normal mode) 14 85 100 mw av dd +dv dd current (standby mode) 15 140 a power dissipation (standby mode) 15 750 w 1 specifications are not production tested but guaranteed by desi gn and/or characterization data at initial product release. 2 see typical performance characteristics. 3 v cm = common-mode voltage = 0 v. 4 specifications before calibration. channel system calibration reduces these errors to the order of the noise. 5 applies after the zero-scale and full-scale calibration. the negative full-sca le error repres ents the remainin g error after re moving the offset and gain error. 6 adc zero-scale self-calibration reduces this error to 10 mv. channel zero-scale system calibration reduces this error to the o rder of the noise. 7 for specified performance. the output data span corresponds to the specified nominal input voltag e range. the adc is functional outside the nominal input voltage range, but the performance might degrade. outside the nominal input voltage range, the ovr bit in the channel status register i s set and the channel data register value depends on the clamp bit in the mode register. see the register and circuit descriptions for more details. 8 the ain absolute voltage of 16.5 v applies for a nominal vbias voltage of +2.5 v. by configuring the bias and ra to rd pins di fferently, the part will work with higher ain absolute voltages as long as the i nternal voltage seen by the multiplexer an d the input buffer is within 200 mv to av dd ? 300 mv. absolute voltage for the ain, bias, and ra to rd pins must never exceed the values specified in the absolute maximum ratings. 9 pin impedance is from the pin to the internal node. in normal circuit configuration, the analog input total impedance is typic ally 108.5 k + 15.5 k = 124 k. 10 for specified performance. part is functional with lower v ref . 11 dynamic current charging the sigma-delt a modulator input switching capacitor. 12 outside the specified calibration range, calibrat ion is possible but the performance may degrade. 13 these logic output levels apply to the mclk out output when it is loaded with a single cmos load. 14 with external mclk, mclkout is disabled (the clkdis bit is set in the m ode register). 15 external mclkin = 0 v or dv dd , digital inputs = 0 v or dv dd , and p0 and p1 = 0 v or av dd.
ad7732 timing specifications table 2. ( a v dd = 5 v 5%; d v dd = 2.7 v to 3.6 v, or 5 v 5%; input lo gic 0 = 0 v; logic 1 = dv dd ; unless otherwise noted.) 1 p a r a m e t e r m i n t y p m a x u n i t test condition s / c o m m e n t s master clock range 1 6.144 mhz t 1 5 0 n s sync pulsewid t h t 2 5 0 0 n s reset pulsewid t h read operation t 4 0 ns cs falling edge to sclk falling edge setup time t 5 2 sclk falling edge to data valid delay 0 6 0 n s dv dd of 4.75 v to 5.25 v 0 8 0 n s dv dd of 2.7 v to 3.3 v t 5a 2, 3 cs falling edge to data valid delay 0 6 0 n s dv dd of 4.75 v to 5.25 v 0 8 0 n s dv dd of 2.7 v to 3.3 v t 6 50 ns sclk high pulsewidth t 7 50 ns sclk low pulsewidth t 8 0 ns cs rising edge aft e r sclk rising edge hold time t 9 4 10 80 ns bus relinquish time after sclk rising edge write operation t 11 0 ns cs falling edge to sclk falling edge setup t 12 30 ns data valid to sc lk rising edge s e tup time t 13 25 ns data valid after sclk rising edg e hold time t 14 50 ns sclk high pulsewidth t 15 50 ns sclk low pulsewidth t 16 0 ns cs rising edge aft e r sclk rising edge hold time 1 sa m p le t e st e d duri n g i n i t i a l relea s e t o en sure com p li a n ce. al l i n put si gn a l s a r e sp eci f i e d wi t h t r = t f = 5 n s (10% t o 90% of dv dd ) a n d t i m e d from a volt a g e lev e l o f 1.6 v. s ee a n d . figure 2 f i g u r e 3 2 these number s ar e measur ed with the loa d circuit o f a n d de f i ne d as the time re quire d fo r the o u tput to cro s s the v ol or v oh li m i t s. figu r e 4 figu r e 4 3 this s p ecif ication is rel e vant onl y if cs goes low while sclk is low. 4 the s e numbe r s are d e rive d f r o m the me as ured time take n by the d a ta o u tput to change 0.5 v whe n lo ad ed with the circuit o f . t h e m e as ured n u mber is then ext r a p ola t ed ba ck t o rem o ve ef fect s o f ch a rgi n g or di sch a rgi n g t h e 50 pf ca p a ci t o r. th i s m e a n s t h a t t h e t i m e s q u ot ed i n t h e ti m ing c h aracteris t ics are the true bus reli n q u i s h t i m e s o f t h e pa rt a n d a s suc h a r e i n depen d en t of ext e rn a l bu s loa d i n g ca pa ci t a n c es. rev. 0 | page 6 of 3 2
ad7732 dout msb lsb cs t 4 t 5a t 5 t 6 t 7 t 9 t 8 sclk f i g u re 2. r e ad c y c l e tim i ng d i ag r a m din msb lsb s cl k cs t 11 t 14 t 15 t 16 t 13 t 12 f i gure 3. wri t e c y c l e tim i ng d i ag r a m i source (200 a at dv dd = 5v 100 a at dv dd = 3v) i sink (800 a at dv dd = 5v 100 a at dv dd = 3v) 1.6v t o output pin 50pf f i gur e 4 . l o a d cir c ui t fo r a c c e ss t i me a n d bus reli nqui sh t i m e rev. 0 | page 7 of 3 2
ad7732 absolute maximum ratings table 3. t a = 25c, unless otherwise no ted. p a r a m e t e r r a t i n g av dd to agn d , dv dd to dgnd C0.3 v to +7 v agnd to dg nd C0.3 v to +0.3 v av dd to dv dd C5 v to +5 v ain to ag nd C50 v to +50 v ra, rb, rc, rd t o agnd C11 v to +25 v bias to agnd C0.3 v to av dd + 0.3 v refin+, refi nC to agnd C0.3 v to av dd + 0.3 v p0, p1 voltage t o agnd C0.3 v to av dd + 0.3 v p0, p1 current ( t max = 70c) 8 ma p0, p1 current ( t max = 85c) 5 ma p0, p1 current ( t max = 105c) 2.5 ma digital input voltage to dgnd C0.3 v to dv dd + 0.3 v digital output v o ltage to dgnd C0.3 v to dv dd + 0.3 v operating tem p erature range C40c to +105c storage temperature range C65c to +150c junction tempe r ature 150c tssop package, power dissi pati on 660 mw ja thermal imp e dance 97.9c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y ca us e p e r m an e n t da ma g e t o t h e de vice . this is a s t r e s s ra t i n g o n ly ; f u nc t i on a l o p e r a t i o n of t h e d e v i c e a t t h e s e or a n y ot h e r c o n d i t i ons ab ove t h o s e i n d i c a te d i n t h e op e r a t i o n a l s e c t i o n of t h i s sp e c if ica t ion is not i m pl i e d. e x p o su re to ab s o lute m a x i m u m r a t i ng c o n d i t i ons for e x te nd e d p e r i o d s m a y af fe c t d e v i c e rel i a b i l it y . rev. 0 | page 8 of 3 2
ad7732 rev. 0 | page 9 of 3 2 typical perf orm ance cha r acte ristics filter word no mis s i ng code s 16 17 18 19 20 21 22 23 24 25 1 2 3 45 6 7 89 1 0 chop = 1 f i gur e 5 . no m i ssing c o des p e r f or ma nc e , choppi ng ena b le d filter word no mis s i ng code s 16 17 18 19 20 21 22 23 24 25 1 2 3 45 6 7 89 1 0 chop = 0 f i gur e 6 . no m i ssing c o des p e r f or ma nc e , c h op pi ng d i sabl ed mclk frequency ? mhz inl ? ppm 0 5 10 15 01234 567 v cm = 0v f i gure 7. t y pic a l in l vs . mclk f r equen c y , 10 v d i ffer e ntial sign al , ain c o mmon-mod e v o ltage = 0 v , bias(+) = bias( C ) = 2. 5 v ain differential voltage ? v inl ? ppm 0 10 20 30 40 50 60 ? 2 0 ? 1 5 ? 1 0 ? 50 51 0 1 5 2 0 mclk = 6.144mhz v cm = 0v f i g u re 8. t y pic a l in l v s . a i n d i f f e r e nt i a l v o lt ag e , a i n co mm on-m ode v o l t ag e = 0 v , mcl k = 6. 144 m h z, bia s (+) = b i as(C ) = 2.5 v ain common-mode voltage ? v inl ? ppm 0 10 20 30 40 50 60 ?15 ? 10 ?5 0 5 10 15 mclk = 6.144mhz f i gur e 9 . t y pi c a l inl vs . ain c o mmo n- mode v o lt age , 1 0 v d i fferential si gnal , mcl k = 6.144 m h z, bias(+) = bias(C ) = 2. 5 v mclk frequency ? mhz av dd + dv dd curre nt ? ma 0 5 10 15 20 01234 567 f i gure 10. t y pic a l s u p p ly cu rrent v s . mclk f r equ e nc y , nor m al o p er at i o n, conve r t i ng
ad7732 rev. 0 | page 10 of 32 output noise and reso lution specification the ad7732 can be operated with chopping enabled or disabled, allowing the adc to be programmed to either optimize the throughput rate and channel switching time or to optimize the offset drift performance. noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. the ad7732 noise performance depends on the selected chopping mode, the filter word (fw) value, and the selected analog input range. the ad7732 noise will not vary significantly with mclk frequency. chopping enabled the first mode, in which the ad7732 is configured with chopping enabled (chop = 1), provides very low noise with lower output rates. table 4 to table 6 show the ?3 db frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. shows the typical output rms noise. table 5 shows the typical effective resolution based on rms noise. table 6 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table 4. typical output rms noise in v vs. conv ersion time and input range with chopping enabled fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) rms noise (v) 127 ffh 2686 372 200 9.6 46 aeh 999 1001 520 15.5 22 96h 499 2005 1040 22.7 17 91h 395 2534 1300 26.1 8 88h 207 4826 2500 39.2 6 86h 166 6041 3100 46.0 2 82h 82 12166 6300 120.0 table 5. typical effective resolution in bits vs. co nversion time and input range with chopping enabled input range/effective resolution (bits) fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) 10 v 0 v to +10 v 5 v 0 v to +5 v 127 ffh 2686 372 200 21.0 20.0 20.0 19.0 46 aeh 999 1001 520 20.3 19.3 19.3 18.3 22 96h 499 2005 1040 19.7 18.7 18.7 17.7 17 91h 395 2534 1300 19.5 18.5 18.5 17.5 8 88h 207 4826 2500 19.0 18.0 18.0 17.0 6 86h 166 6041 3100 18.7 17.7 17.7 16.7 2 82h 82 12166 6300 17.3 16.3 16.3 15.3 table 6. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping enabled input range/peak-to-peak resolution (bits) fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) 10 v 0 v to +10 v 5 v 0 v to +5 v 127 ffh 2686 372 200 18.1 17.1 17.1 16.1 46 aeh 999 1001 520 17.4 16.4 16.4 15.4 22 96h 499 2005 1040 16.9 15.9 15.9 14.9 17 91h 395 2534 1300 16.7 15.7 15.7 14.7 8 88h 207 4826 2500 16.2 15.2 15.2 14.2 6 86h 166 6041 3100 15.8 14.8 14.8 13.8 2 82h 82 12166 6300 15.0 13.4 13.4 12.4
ad7732 rev. 0 | page 11 of 32 chopping disabled the second mode, in which the ad7732 is configured with chopping disabled (chop = 0), provides faster conversion time while still maintaining high resolution. table 7 to table 9 show the ?3 db frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. table 7 shows the typical output rms noise. table 8 shows the typical effective resolution based on the rms noise. table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table 7. typical output rms noise in v vs. conve rsion time and input range with chopping disabled fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) rms noise (v) 127 7fh 1357 737 670 13.2 92 5ch 992 1008 920 15.5 44 2ch 492 2032 1850 22.7 35 23h 398 2511 2290 26.3 16 10h 200 4991 2500 39.0 8 08h 117 8545 7780 57.0 3 03h 65 15398 14000 132 table 8. typical effective resolution in bits vs. conv ersion time and input range with chopping disabled input range/effective resolution (bits) fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) 10 v 0 v to +10 v 5 v 0 v to +5 v 127 7fh 1357 737 670 20.5 19.5 19.5 18.5 92 5ch 992 1008 920 20.3 19.3 19.3 18.3 44 2ch 492 2032 1850 19.7 18.7 18.7 17.7 35 23h 398 2511 2290 19.5 18.5 18.5 17.5 16 10h 200 4991 2500 19.0 18.0 18.0 17.0 8 08h 117 8545 7780 18.4 17.4 17.4 16.4 3 03h 65 15398 14000 17.2 16.2 16.2 15.2 table 9. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping disabled input range/peak-to-peak resolution (bits) fw conversion time register conversion time (s) output data rate (hz) ?3 db frequency (hz) 10 v 0 v to +10 v 5 v 0 v to +5 v 127 7fh 1357 737 670 17.6 16.6 16.6 15.6 92 5ch 992 1008 920 17.4 16.4 16.4 15.4 44 2ch 492 2032 1850 16.8 15.8 15.8 14.8 35 23h 398 2511 2290 16.6 15.6 15.6 14.6 16 10h 200 4991 2500 16.1 15.1 15.1 14.1 8 08h 117 8545 7780 15.5 14.5 14.5 13.5 3 03h 65 15398 14000 14.3 13.3 13.3 12.3
ad7732 pin conf igurations and f u ncti ona l descriptions top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad7732 bias0(+) ain0(+) ain1(+) bias1(+) rb ra sync/p1 sclk mclkin cs p0 av dd reset bias0(?) ain0(?) ain1(?) bias1(?) rc rd refin(+) dgnd dv dd din dout refin(? ) agnd rdy mclkout f i gure 11. 28-l ead t ssop p0 sync/p1 ain0(+) ain1(+) ain0(? ) bias0(+) bias0(? ) ain1(? ) bias1(+) bias1(? ) ra rb rc rd sclk din dout cs reset rdy dgnd mclkin mclkout agnd av dd dv dd av dd dv dd 7r r=15.5k ? 2r r r r 7r 7r 7r 2r 2r 2r buffer reference detect refin( ? ) refin(+) ad7732 24-bit ?? adc serial interface control logic clock generator calibration circuitry i/o port mux f i g u re 12. bl ock d i ag r a m table 10. pin function des c riptions28-lead tsso p pin no. mnemonic description 1 sclk serial clock. schmitt triggered lo gic input. an external serial c l ock is applied to this input to transfer serial data to or from the ad7732. 2 mclkin master clock signal for the adc. this can be provided in the form of a crystal/ resonator or ex ternal clock. a crystal/ resonator can be tied across the mclkin and mclk out pins. alternatively, the mclkin pin can be dr iven with a cmos compa t ible clock and mclkout left u n connected. 3 mclkout when the maste r clock for the d evice is a crystal/ resonator, the crystal/ resonator is connected between mclkin and mclkout. i f an external c l oc k is app l ied to the mclkin, mclkout provides an i n verted clock s i gnal or can be switched off to reduce the device pow er consumptio n. mclk out is capabl e of driving one cmos load. 4 cs chip select. acti ve low schm itt triggered logi c in put with an internal pull-up resi stor. with this input hardwired low, t h e ad7732 ca n operate in its 3- wire interface m o de using sclk, din, and dout. cs can be used to sele ct the d evice in systems with m o re than one device on the serial bus. it can also be used as an 8-bit frame synchroni z ation signal. 5 reset schmitt trigger e d logic input. active low inpu t that resets the control logic, int e rface logic, d i gital filter, anal og mod u lator, and al l on- c hip registers of the part to pow er-on status. effectively, everything on the part exce pt the clock osci llator is reset whe n the reset pin is exer cised. 6 a v dd analog positive supply voltage. 5 v to ag nd nominal. 7 p0 digital input/ output. the pin dir e ction is de termined by the p0 dir bit; the digi t a l value can be read/ w ritten as the p0 bit in the i/o port register. the digital voltage is referenced to analog supplie s . when configur e d as an input, the pin should be tied high or lo w. rev. 0 | page 12 of 32
ad7732 rev. 0 | page 13 of 32 pin no. mnemonic description 8 sync /p1 sync /digital input/digital output. the pin dire ction is determined by the p1 dir bit; the digital value can be read/written as the p1 bit in the i/o port register. when the sync bit in the i/o port register is set to 1, the sync /p1 pin can be used to synchronize the ad7732 modulator and digital filter with other devices in the system. the digital voltage is referenced to analog supplies. when configured as an input, the pin should be tied high or low. 9 ra ra, in association with rb and bias0(+), can be used to level shift the positive analog input 0. in normal circuit configurat ion, this pin is left open circuit. 10 rb rb, in association with ra and bias0(+), can be used to level shift the positive analog input 0. in normal circuit configurat ion, this pin is left open circuit. 11 bias1(+) this input is used to level shift the positive analog input 1. this signal is used to ensure that the differential signal seen by the inte rnal buffer amplifier is within its common- mode range. bias pins will no rmally be connected to 2.5 v. 12 ain1(+) positive analog input channel 1. 13 ain0(+) positive analog input channel 0. 14 bias0(+) voltage bias for positive analog input 0. this pin has the same function as bias1(+). 15 bias0(?) voltage bias for negative analog input 0. this pin has the same function as bias1(+). 16 ain0(?) negative anal og input channel 0. 17 ain1(?) negative anal og input channel 1. 18 bias1(?) voltage bias for negative analog input 1. this pin has the same function as bias1(+). 19 rc rc, in association with rd and bias0(?), can be used to level shift the negative analog input 0. in normal circuit configurat ion, this pin is left open circuit. 20 rd rd, in association with rc and bias0(?), can be used to level shift the negative analog input 0. in normal circuit configurat ion, this pin is left open circuit. 21 refin(+) positive terminal of the differential reference input. refin(+) voltage potential can lie anywhere between av dd and agnd. in normal circuit configuration, this pin should be connected to a 2.5 v reference voltage. 22 refin(?) negative terminal of the differential referenc e input. refin(?) voltage potential can lie anywhere between av dd and agnd. in normal circuit configuration, this pin should be connected to a 0 v reference voltage. 23 agnd ground reference point for analog circuitry. 24 rdy logic output. used as a status output in both conversion mo de and calibration mode. in conversion mode, a falling edge on this outp ut indicates that either any channel or all channels have unread data available, accordin g to the rdyfn bit in the i/o port register. in calibration mode, a falling edge on this output indicates that calibration is complete (see the digital interface description section for more details). 25 dout serial data output with serial data being read from the outp ut shift register on the part. this output shift register can contain info rmation from any ad7732 register, depending on the address bits of the communications register. 26 din serial data input (schmitt triggered) with serial data bein g written to the input shift register on the part. data from this input shift register is transferred to any ad7732 register, depending on the address bits of the communications register. 27 dv dd digital supply voltage, 3 v or 5 v nominal. 28 dgnd ground reference point for digital circuitry.
ad7732 rev. 0 | page 14 of 32 register description table 11. register summar y register addr dir b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 ( h e x ) default v a l u e c o m m u n i c a t i o n s 0 0 w 0 r/w 6-bit register ad d r ess i/o port 01 r/w p0 p1 p0 dir p1 dir rdyfn 0 0 sync p 0 p i n p 1 p i n 1 1 0 0 0 0 revision 02 r chip revision code chip generic code x x x x 0 1 0 0 test 03 r/w 24-bit manufacturing test regis t er a d c s t a t u s 0 4 r C C C C C r d y 1 C r d y 0 0 0 0 0 0 0 0 0 checksum 05 r/w 16-bit checksu m register adc zero-scale calibrati o n 06 r/w 24-bit adc zero-scale ca libratio n register 8 0 0 0 0 0 h adc full-scale 07 r/w 24-bit adc full-scale register 8 0 0 0 0 0 h channe l data 1 08, 0a r 16-/24-bit data registers 8 0 0 0 h channe l zero-s cale ca l. 1 10, 12 r/w 24-bit channel zero-scale c a libration registers 8 0 0 0 0 0 h channe l full-sc ale cal. 1 18, 1a r/w 24-bit channel f u ll-scale c a libr a t ion registers 2 0 0 0 0 0 h channe l status 1 2 0 , 2 2 r 0 c h 1 0 0 / p 0 r d y / p 1 n o r e f s i g n o v r channe l n u m b e r 0 0 0 0 0 channe l setup 1 2 8 , 2 a r / w 0 0 0 s t a t o p t e n a b l e 0 r n g 1 r n g 0 0 0 0 0 0 0 0 0 channe l conver sion time 1 30, 32 r/w chop fw (7-bit filter word) 1 1 1 h mode 2 38, 3a r/w md2 md1 md0 clkdis dump cont rd 24/16 bit c lamp 0 0 0 0 0 0 0 0 1 bit 1 in the co mmunicatio n re gis t e r s p e c if ie s the channe l numbe r o f the regis t e r be ing acce ss e d . 2 th ere i s on ly on e m o de regi st e r, a l t h ough t h e m o de reg i st er ca n be a cces s e d i n on e o f t w o a d d r es s loca t i on s. th e a ddre s s us ed t o wri t e t h e m o d e r e gi st e r speci f i e s t h e ad c ch a n n e l on w h i c h t h e m o de wi l l be a ppli e d . on ly a d dre s s 38h m u st be use d for rea d i n g fr om t h e m o d e r e gi s t er. table 12. ope r ational mode summary m d 2 m d 1 m d 0 m o d e 0 0 0 idle m o d e 0 0 1 continuous conversion m o d e 0 1 0 single conver si on m o d e 0 1 1 pow e r-down (standby) m o d e 1 0 0 adc zero-scale s e l f - c a l i b r a t i o n 1 0 1 for f u t u r e u s e 1 1 0 channe l zero-s cale system cali bration 1 1 1 channe l full-scale system calibration table 13. in p u t range su mmary rng1 rng0 nominal input voltage range 0 0 1 0 v 0 1 0 v to +10 v 1 0 5 v 1 1 0 v to +5 v
ad7732 register a ccess the ad7732 is co nf igura b le thr o ug h a s e r i es o f r e g i s t ers. s o m e o f th em conf igur e a nd co n t r o l gen e ral ad7732 f e a t ur es, while ot he rs are sp e c i f ic to e a ch chan ne l. t h e re g i ste r d a t a wi d t hs va r y f r o m 8 b i ts t o 24 b i ts. al l r e g i s t ers a r e access ed thr o ug h t h e co m m un ica t i o n s r e gi s t e r , i . e . , a n y co m m un ica t io n t o th e ad7732 m u st sta r t wi t h a wr i t e t o th e comm unica t ion s r e g i s t er sp e c if y i ng w h ic h re g i ste r wi l l b e subs e q u e n t ly re ad or wr it te n. communi c ations register 8 b i t s , w r i t e-o n l y re g i s t er , a d d r e s s 00h a l l c o mm u n i c a t ions to t h e p a r t m u st st ar t w i t h a wr ite o p era t ion t o t h e co mm uni c a t ion s r e g i s t er . th e da t a wr i t t e n t o t h e comm unic a t io n s r e g i s t er de t e r m in e s w h et her t h e subs e q uen t op e r a t io n wi l l b e a r e ad o r wr i t e and t o w h ich r e g i ster t h is o p e r a t io n wi l l b e di r e c t e d . t h e dig i t a l in ter f ace defa u l ts t o exp e c t wr i t e o p era t i o n t o t h e co mm unica t io n s re g i ste r af te r p o we r - on , af te r re s e t , or af te r t h e s u b s e q u e n t re a d o r wr i t e o p era t i o n t o t h e s e le c t e d r e g i s t er is com p let e . i f t h e in t e r f ace s e q u e n ce is lost, t h e p a r t ca n b e r e s e t b y wr i t in g a t le ast 32 s e r i a l cl o c k c y cles wi t h din hig h an d cs lo w . (n o t e tha t al l o f t h e p a r t s, in cl udin g t h e mo d u l a t o r , f i l t er , in t e r f ace , and al l r e g i s t ers a r e r e s e t in t h is cas e .) re m e m b er t o k e ep d i n lo w while r e adin g 3 2 b i ts o r m o r e ei th er in co n t in u o us r e ad m o de o r w i th th e d u m p b i t a n d 2 4/ 1 6 b i t i n th e m o d e r e gi s t e r s e t . bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m n e m o n i c 0 r/w 6-bit register ad d r ess b i t m n e m o n i c d e s c r i p t i o n 7 0 t h is bit must be 0 for proper op eration. 6 r/w a 0 in this bit indicates that the nex t operation will be a write to a specified reg i ster. a 1 in this bit indicates that the next operation wil l be a read from a spe c ified register. 5C0 addres s ad d r ess specifying to which regi ster the read or write ope ratio n will b e d i rected . for channe l spe c ific registers, bit 1 specifies th e channe l numb er. when the subsequent op era t ion writes to the mode register, bit 1 specifies the channe l sele cted for operation d e termined by the mode register value (see table 14). table 1 4 . bit 2 bit 1 bit 0 channel input 0 0 0 0 ain0(+) C ain0 ( C ) 0 1 0 1 ain1(+) C ain1 ( C ) rev. 0 | page 15 of 32
ad7732 i/o port register 8 b i t s , re ad/w r i t e re g i s t er , a d d r e s s 01h, d e fa u l t v a l u e 30h + d i g i t a l i n p u t v a l u e 4 0 h the b i ts in this r e g i s t er a r e us e d t o co nf igur e and acces s t h e dig i tal i/o p o r t o n the ad7732. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic p0 p1 p0 dir p1 dir rdyfn 0 0 sync d e f a u l t p 0 p i n p 1 p i n 1 1 0 0 0 0 b i t m n e m o n i c d e s c r i p t i o n 7, 6 p0, p1 when the p0 and p1 pins are co nfigured as outputs, th e p0 and p1 bits determi n e the pins out p ut level. when the p0 and p1 pi ns are co nfigured as inputs, the p0 an d p1 bits r e flect the current input level on the pins. 5, 4 p0 dir, p1 dir these bits determine whether t h e p0 and p1 pins are co nfigured as inputs or o utputs. when set to 1, the corres ponding pin wil l be an i n put; when reset to 0, the corresp onding pin wi ll be an output. 3 r d y f n this bit is used t o control the function of the rdy pi n on the ad7732. when this bit is reset to 0, the rdy pin goes lo w when any channe l has unread d a ta . w h en this bit is set to 1, the rdy pin w i ll on ly go low if all enabl e d channe ls have unre ad data. 2, 1 0 t h ese bits must be 0 for proper operatio n . 0 s y n c this bit enables the sync pin function. by default, thi s bit is 0 and sync /p1 can be used as a digital i/o pin. when the sync bit is set to 1, the sync pin can be used to synchroni z e the ad7732 modulator and digital filter with other d evices in the sy stem. revision register 8 b i t s , re ad-o n l y re g i s t er , a d d r es s 02h, d e fa u l t v a l u e 04h + ch ip re v i s i o n 1 0 h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic chip revision code chip generic code defau l t x x x x 0 1 0 0 b i t m n e m o n i c d e s c r i p t i o n 7C4 chip revision code 4-bit factory chip revision code 3C0 chip generic code on the ad7732, these bits wi ll re ad back as 04h. test regis t er 24 b i ts, rea d /w r i t e re gis t er , a d d r e s s 03h this r e g i s t er is us e d fo r t e s t in g t h e p a r t in t h e ma n u fac t ur in g p r o c es s. th e us er m u s t n o t chan g e t h e def a u l t co nf igura t io n of th i s r e gi s t e r . rev. 0 | page 16 of 32
ad7732 adc status register 8 b i t s , re ad-o n l y re g i s t er , a d d r es s 04h, d e fa u l t v a l u e 00h i n con v ersio n m o de s, t h e r e g i st er b i ts r e f l e c t t h e i ndivi d u al cha nne l st a t us. w h e n a con v ersion is co m p le t e , t h e co r r es p o n d i n g chan nel da t a r e g i s t er is u p da te d and t h e co r r es p o n d ing rd y b i t is s e t t o 1. w h e n t h e cha n n e l da t a r e g i s t er is r e ad , t h e co r r es p o n d ing b it i s re s e t to 0. th e b i t is als o r e s e t t o 0 w h en n o r e ad o p era t i o n has t a k e n pl ace an d t h e r e s u l t o f t h e n e xt con v ersio n is b e i n g u p da te d t o th e c h a n n e l da t a r e g i s t er . w r i t in g t o t h e mo de r e g i s t er r e s e ts al l t h e b i ts t o 0. i n cal i b r a t ion mo des, al l t h e r e g i s t er b i ts a r e r e s e t t o 0 w h i l e a cal i b r a t ion is in p r og r e s s ; al l t h e r e g i s t er b i ts a r e s e t t o 1 w h en t h e ca lib r a t ion is com p let e . the rd y p i n o u t p u t is r e la t e d t o th e co n t en t o f the ad c s t a t us r e g i s t er as def i ned b y th e rd yf n b i t in t h e i/o p o r t r e g i s t er . the r d y0 b i t c o r r es p o n d s t o t h e dif f er en t i al i n p u t 0, and t h e rd y1 b i t co r r es p o n d s t o t h e dif f er en t i al i n p u t 1 . bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m n e m o n i c C C C C C r d y 1 C r d y 0 d e f a u l t 0 0 0 0 0 0 0 0 chec ksum register 16 b i ts, rea d /w r i t e re gis t er , a d d r e s s 05h this r e g i st er is des c r i b e d i n t h e us i n g t h e ad77 32/a d 7 7 3 4 /ad7 73 8 che c ks u m re g i s t er a p plica t io n n o te ( w w w . a nalog.com/u p lo ade d f i l e s/a p p l ic a t ion_ n o t e s/7175187 6 an626_0. p d f ). adc zero-scale calibration register 2 4 b i ts , re a d /w ri t e re gis t e r , a d d r e s s 06 h, de fa u l t v a l u e 800 00 0h the r e g i s t er h o l d s t h e ad c zero-s cale cal i b r a t i o n co ef f i cien t. the val u e i n t h i s r e g i s t er is us e d in con j u n c t ion w i t h t h e va l u e in t h e ad c f u l l - s c ale calib r a t ion r e g i s t er and t h e co r r es p o n d i n g c h a n n e l zer o -s c a le a nd c h a n ne l f u l l -s cale cal i b r a t io n reg i s t ers to s c ale dig i t a l l y al l cha n n e ls con v ersio n r e s u l t s. th e va l u e in t h is r e g i s t er is u p da te d a u t o ma t i c a l l y fol l o w in g t h e exe c u t io n o f a n ad c zer o -s c a le s e lf-ca l ib ra t i on. w r i t in g t h is r e g i st er is p o s s i b le in t h e idle mo de o n l y ( s ee t h e c a lib r a t io n s e c t ion f o r more d e t a i l s ) . adc full-s cale register 2 4 b i ts , re a d /w ri t e re gis t e r , a d d r e s s 07 h, de fa u l t v a l u e 800 00 0h this r e g i s t er h o lds t h e ad c f u l l -s cale co ef f i cien t. th e us er is ad vi s e d n o t to cha n ge t h e def a u l t co nf igur a t ion o f t h is r e g i ster . channel data registers 16 b i t / 2 4 b i t, rea d -o n l y re g i s t ers, a d d r es s 0 8 h, 0a h, d e fa u l t w i d t h 1 6 b i ts, def a ul t v a l u e 80 00 h th e s e r e g i s t ers co n t a i n t h e m o st u p -t o-da t e con v ersio n r e s u l t s co r r esp o n d in g to e a ch a n a l og in p u t cha n ne l. the 16-b i t o r 24- b i t da t a wid t h c a n be co nf igur e d b y s e t t in g t h e 16 b i t/24 b i t in t h e m o de r e g i s t er . th e r e l e van t rd y b i t i n t h e cha n n e l st a t us r e g i s t er g o es hi g h w h e n t h e r e su l t is u p da t e d . th e r d y b i t wi l l re tu r n l o w onc e t h e d a t a re g i ste r re a d i n g h a s b e g u n . t h e rd y p i n c a n b e conf i g ur e d to i n di ca te w h en an y channel has unr e a d da ta o r wai t s u n til al l ena b le d cha n n e ls ha ve unr e ad da t a . i f an y cha n n e l d a t a r e g i st er r e ad o p er a t io n is in p r og r e ss w h e n a ne w r e s u l t is u p da t e d , n o u p da te o f th e da ta r e g i s t er wil l o c c u r . this a v o i ds h a v i n g c o r r u p te d d a t a . re ad in g t h e st a t us r e g i sters ca n be as soci a t e d w i th r e a d i n g t h e da ta r e gis t e r s in th e d u m p m o d e . re ad in g t h e st a t us r e g i st ers is a l wa y s ass o ci a t e d wi t h r e ad in g t h e da t a r e g i s t ers in t h e con t i n uo us r e ad m o de ( s e e t h e dig i t a l i n ter f ace d e s c r i p t io n s e c t io n for m o r e det a i l s). rev. 0 | page 17 of 32
ad7732 channel z e ro-scale calibratio n register s 24 b i ts, rea d /w r i t e re g i s t ers, a d d r es s 1 0 h, 1 2 h, d e fa ul t v a l u e 80 00 00h h e s e r e g i s t ers h o ld t h e p a r t ic u l a r cha n n e l er o -s cale calib r a t ion co ef f i cien ts h e v a l u e in t h es e r e g i st ers is us e d i n co n u n c t io n i t h t h e val u e i n t h e co r r es p o n d ing cha n n e l f u l l - s c ale cal i b r a t ion r e g i s t er , t h e ad c er o -s cale cal i b r a t ion r e g i s t er , a nd t h e ad c f u l l - s cale r e g i s t er t o dig i t a l l y s c ale t h e p a r t ic u l a r cha n n e l con v ersio n r e s u l t s h e val u e in t h is r e g i st er is u p d a te d a u t o ma t i c a l l y fol l o in g t h e ee c u t io n o f a cha n ne l er o -s c a le sys t em cal i b r a t ion he f o r m a t o f th e c h ann e l er o -s cale calib r a t ion r e g i s t er is a sig n b i t and 22 b i ts un sig n e d va l u e w r i t in g t h is r e g i st er is p o s s i b le in t h e idle mo de o n l y s ee t h e c a lib r a t io n s e c t ion f o r more d e t a i l s channel f u ll-sc a le c a libration registers 24 b i t s , rea d /w r i t e re g i s t ers, a d d r es s 1 8 h, 1a h, d e fa u l t v a l u e 20 00 00h h e s e r e g i s t ers h o ld t h e p a r t ic u l a r cha n n e l f u l l - s cale cal i b r a t ion co ef f i cien ts he val u e i n t h es e r e g i s t ers is us e d in co n u n c t ion i t h t h e val u e i n t h e co r r es p o ndin g chann e l e r o -s cale ca lib r a t ion r e g i ster , t h e a d c ero -s ca le ca l i b r a t i o n r e g i ster , an d t h e ad c f u l l - s c a le r e g i s t er t o di g i t a l l y s c ale t h e p a r t ic u l a r cha n n e l con v ers i o n r e s u l t s h e val u e in t h is reg i s t er is u p da t e d a u t o ma tic a ll y f o ll o i n g th e e ecu t i o n o f a c h a n n e l full - s c a l e sy st em ca lib r a t i o n w r i t i n g t h is r e g i st er is p o ssib le in t h e i d le m o d e o n ly s e e t h e c a l i b r a t io n s e c t io n fo r m o re det a i l s channel status regi sters 8 b i ts, re ad-o n l y re g i s t er , a d d r es s 20h, 2 2 h, d e fa u l t v a l u e 2 0 h cha n n e l n u m b er h es e r e g i s t ers co n t a i n individ u al c h a n ne l s t a t us inf o r m a t io n a nd s o m e g e n e r a l ad7732 sta t u s inf o r m a t io n readin g t h e s t a t u s r e gi s t e r s ca n b e as s o c i a t e d i t h r e adin g t h e da t a reg i s t ers in t h e d u m p mo de re adi n g t h e s t a t us r e g i s t ers is al a ys as s o c i a t e d i t h r e ad in g th e da t a r e g i s t ers in t h e co n t i n uo us r e ad m o de s e e t h e dig i t a l i n ter f ace d e s c r i p t ion s e c t io n fo r m o r e det a ils bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m n e m o n i c 0 c h 1 0 0 / p 0 r d y / p 1 n o r e f s i g n o v r d e f a u l t channe l n u m b e r 0 0 0 0 0 b i t m n e m o n i c d e s c r i p t i o n 7 C 5 c h 1 these bits reflec t the channel nu mber. this can b e used for current channel iden tification and ea sier operatio n of the dump mode and continuous read mode. 4 0 / p 0 when the status option bit of the corresp ond i n g channel setup register is reset to 0, this bit is read as a zero. when the status option bit is set to 1, this bit reflects the state of the p0 pin, whether it is configured as an input or an output. 3 r d y / p 1 when the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected chan ne l rdy bit in the adc status register. when the status option bit is set to 1, this bit reflects the state of the p1 pin, whether it is co nfigured as an input or an output. 2 n o r e f this bit indicates the reference input status. if th e voltage between the refi n( +) and refin( C) pins is le ss than noref, the trigger voltage and a conver sion i s ex ecuted, then the noref bit goes to 1. 1 sign the voltage pol arity at the analog input. it will be 0 for a positi ve voltage and 1 for a negative voltage. 0 o v r this bit reflects either the overr a nge or the underrang e on the analog input. the bit is set to 1 when the analog input voltage goes over or under the nominal vo ltage ra nge (see th e analog inputs ext e nded voltage range section). rev. 0 | page 18 of 32
ad7732 channel setup registers 8 b i t s , re ad/w r i t e re g i s t er , a d d r e s s 28h, 2a h, d e fa u l t v a l u e 00h th e s e r e g i s t ers a r e us e d t o co nf igur e t h e s e le c t e d cha n ne l , t o conf igur e i t s in p u t v o l t a g e ra n g e , a nd t o s e t u p t h e co r r es p o n d i ng c h an nel st a t u s re g i ste r . bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m n e m o n i c 0 0 0 s t a t o p t e n a b l e 0 r n g 1 r n g 0 d e f a u l t 0 0 0 0 0 0 0 0 b i t m n e m o n i c d e s c r i p t i o n 7C5 0 t h ese bits must be 0 for proper operatio n . 4 s t a t o p t status option. when this bit is set to 1, the p0 a n d p1 bits in the channel st atus register will ref l e c t the state of the p0 and p1 pi ns. when this bit is reset to 0, th e rdy bit in the channel status register will ref l e c t the channel corresponding to the rdy bit in the adc status r e gister. 3 e n a b l e channel enable. set this bi t to 1 to enable the channel in the continuous conversi on mod e . a sin g le conver sion wi ll t a ke pl ace regar d less of this bits value. 2 0 t h is bit must be 0 for proper op eration. 1C0 rng1Crng 0 this is the channel input voltag e range (see tab l e 15). table 1 5 . rng1 rng0 nominal input voltage range 0 0 1 0 v 0 1 0 v to +10 v 1 0 5 v 1 1 0 v to +5 v channel conversion time registers 8 b i t s , re ad/w r i t e re g i s t er , a d d r e s s 30h, 3 2 h, d e fa u l t v a l u e 9 1 h the con v ersio n t i me r e g i s t ers e n a b le o r dis a b l e ch o p pin g and c o nf igur e t h e dig i t a l f i l t er fo r a p a r t ic u l a r cha nne l . this r e g i st er val u e a f fe c t s t h e con v ersio n t i me , f r e q uen c y r e s p o n s e , and no is e p e r f o r ma nce o f t h e ad c. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic chop fw (7-bit filter word) d e f a u l t 1 1 1 h b i t m n e m o n i c d e s c r i p t i o n 7 chop choppi ng enabl e bit. set to 1 to a pply ch oppi ng mode for a particular chan nel. 6 C 0 f w chop = 1, singl e convers i on or continuous con version with on e channe l ena b l e d. conversi on tim e (s) = (fw 1 28 + 248)/mclk frequency (mhz), the fw range i s 2 to 127. chop = 1, continuous conver si on with two cha nnels e n ab led . conversi on tim e (s) = (fw 1 28 + 249)/mclk frequency (mhz), the fw range i s 2 to 127. chop = 0, singl e convers i on or continuous con version with on e channe l ena b l e d. conversi on tim e (s) = (fw 6 4 + 206)/mclk f r equency (mhz), the fw range is 3 to 127. chop = 0, continuous conver si on with two cha nnels e n ab led . conversi on tim e (s) = (fw 6 4 + 207)/mclk f r equency (mhz), the fw range is 3 to 127. rev. 0 | page 19 of 32
ad7732 mode reg i ster 8 b i t s , re ad/w r i t e re g i s t er , a d d r e s s 38h, 3a h, d e fa u l t v a l u e 00h the m o de r e g i st er co nf igur es t h e p a r t an d det e r m in es i t s o p er a t in g m o de . w r i t in g t o t h e m o de r e g i s t er cle a rs t h e ad c s t a t us reg ist e r , s e ts th e rd y p i n to a lo g i c hig h le vel, ex i t s a l l c u r r en t o p er a t io n s , and st ar ts t h e m o de sp e c if ie d b y t h e mo de b i ts. the ad7732 con t a i n s o n l y on e m o de r e g i s t er . bi t 1 o f th e addr es s is us ed f o r wr i t in g t o th e mo de r e g i s t er t o s p e c if y th e c h a n ne l se l e ct e d f o r th e o p e r a t i o n d e t e rm in ed b y th e md 2 t o md 0 b i t s . o n l y th e addr es s 38 h m u s t be us e d f o r r e adin g f r o m t h e m o de r e g i s t er . bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m n e m o n i c m d 2 m d 1 m d 0 c l k d i s d u m p c o n t r d 2 4 / 1 6 b i t c l a m p d e f a u l t 0 0 0 0 0 0 0 0 b i t m n e m o n i c d e s c r i p t i o n 7 C 5 m d 2 C m d 0 mode bits. these three bits determine the ad7732 operation m o de. writing a new value to the mode bits will exit the part from the mode in which it has bee n operating and place it in the n e wly requested mode immediately. the function of the mode bits is described in mor e detail below. 4 c l k d i s master clock ou tput disable. when this bit is se t to 1, the maste r clock i s disab l e d from appearin g at the mclkout pin and the mclkout pin is in a high impedan ce stat e. this allows turning off the mc lkout as a power saving fe ature. when using an external clock on mclkin, the ad7732 co ntinues to have internal clocks and will c o nvert normal ly regard less of the clk d is bit state. wh en using a crystal osc i ll ator or c e ramic resonator across the mclkin and mc lkout pin s , the ad7732 clock is sto pped and no conver sions can take place when the clkdis bit is active. the ad7732 digita l interface can still be acce ssed using the sclk pin. 3 d u m p dump mode. w h en this bit is res e t to 0, the channel status regis t er and channel d a ta register wil l be ad d r essed and read separate ly. when the dum p bit is set to 1, the chann e l stat us register will b e follo wed immediately by a read of the channel data register regard less of whether the sta tus or data register has been addressed through the communication register. the co ntinuous read mod e will always be d u mp mod e reading of the channe l status and data register, rega rdless of th e dump bit value (see the digital interface description sect ion for more details). 2 c o n t r d when this bit is set to 1, the ad 7732 will ope rate in the continuous read mode (see the digital interface description sect ion for more details). 1 2 4 / 1 6 b i t the channel data register data width selection bit. when set to 1, the channel d a ta registers wil l be 24 bits wid e . when set to 0, the channe l d a ta registers will b e 16 bits w i d e . 0 c l a m p this bit determines the chan nel data registers value when the a n alog in put voltage is outside the nomina l input voltage range. when the clamp bit is set to 1, th e channel d a ta register will b e d i gitally clamped either to all 0s or a ll 1s when the ana l o g input voltage go es outside the nomina l inp ut voltage range. when the clamp bit is reset to 0, the data registers reflect the analog in put vo ltage even o utside the nominal vo ltage range (see the analog inputs ex tended voltage range section). md2 md1 md0 mo de addres s use d f o r mo de register write specifi e s: 0 0 0 i d l e m o d e 0 0 1 c o n t i n u o u s conversion m o d e th e first channel to start converting 0 1 0 single conver si on mode channe l to convert 0 1 1 p o w e r-down (standby) m o d e 1 0 0 a d c zero-scale s e l f - c a l i b r a t i o n channe l conver sion time used for the adc self-calibration 1 0 1 f o r f u t u r e u s e 1 1 0 channe l zero-s cale system cali bration channe l to cali brate 1 1 1 channe l full-sc ale system calib r ation channe l to cali brate rev. 0 | page 20 of 32
ad7732 rev. 0 | page 21 of 32 md2 md1 md0 operating mode 0 0 0 idle mode the default mode after power-on or reset. the ad7732 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 continuous co nversion mode the ad7732 performs a conversion on the specified channel. after the conversion is comp lete, the relevant channel data register and channel status register are updated, the relevant rdy bit in th e adc status register is set, and the ad7732 continues converting on the next enabled channel. the part will cycle thro ugh all enabled channels until it is put into another mode or reset. the cycle period will be the sum of all enabled channels? conversion times, set by the corresponding channel conversion time registers. 0 1 0 single conversion mode the ad7732 performs a conversion on the specified channel. after the conversion is comp lete, the relevant channel data register and channel status register are updated, the relevant rdy bit in th e adc status register is set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7732 returns to idle mode. requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 power-down (standby) mode the adc and the analog front end (interna l buffer) go into the power-down mode. the ad7732 digital interface can still be accessed. the clkd is bit works separately, an d the mclkout mode is not affected by the power-down (standby) mode. 1 0 0 adc zero-scale self-calibration mode a zero-scale self-calibration is performe d on internally shorted adc inputs. after the calibration is complete, the cont ents of the adc zero-scale calibration re gister are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7732 returns to idle mode. 1 0 1 for future use. 1 1 0 channel zero-scale system calibration mode a zero-scale system calibration is performed on the selected channel. an external system zero-scale voltage should be provided at the ad7732 analog input and should remain stable for the duration of the calibration. after the calibration is complete, the contents of the correspon ding channel zero-scale calibration register are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7732 returns to idle mode. 1 1 1 channel full-scale system calibration mode a full-scale system calibration is performed on the selected channel. an external system full-scale voltage should be provided at the ad7732 analog input and this voltage should re main stable for the duration of the calibration. after the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7732 returns to idle mode.
ad7732 rev. 0 | page 22 of 32 digital i n terfa c e descri ption hardware the ad7732 s e r i al in ter f ace can b e co nn ec ted t o th e h o s t de vice v i a t h e s e r i al in ter f ace in s e v e ral dif f er en t w a ys. the cs p i n can be us ed t o s e lec t t h e ad7732 as one o f s e v e ral cir c ui ts co nn e c te d t o t h e h o st s e r i a l in ter f ace . w h e n cs is hig h , th e ad7732 ig no r e s th e scl k and d i n sig n als a nd t h e d o ut p i n g o e s t o th e h i gh im p e da n c e s t a t e . w h en th e cs sig n al is n o t used , co nn ect t h e cs pi n to d g n d . the rd y p i n can b e p o l l e d fo r hig h - t o - lo w t r a n si t i on o r can dr i v e t h e h o st de v i ce i n t e r r u p t i n p u t t o indic a te t h a t t h e ad7732 has f i nis h e d t h e s e lec t ed o p er a t io n and/o r n e w da ta f r o m th e ad77 32 is a v a i la b l e . the h o s t sys t em ca n als o wai t a desig n a t e d t i me a f ter a g i ve n comman d is wr i t ten to t h e d e vice bef o r e r e ading. al t e r n a t i v e l y , the ad7732 s t a t u s ca n be p o l l ed . wh e n t h e rd y p i n is n o t us e d in the sys t em, i t sh ou ld be lef t as an op e n c i rc u i t . ( n ote t h a t t h e rd y pi n i s a l w a y s an a c t i ve dig i t a l o u tp u t , i . e., i t ne ver go es in to a hig h im p e dan c e st a t e.) the res e t p i n can be us ed t o r e s e t t h e ad7732. w h en n o t used , co nn ect t h i s p i n t o d v dd . the ad7732 in ter f ace ca n be r e d u ced t o j u st two wir e s co nne c t in g t h e din an d d o u t p i ns to a sin g l e b i d i r e c t io na l d a t a li ne. t h e s e co nd sig n a l i n t h is 2- wir e co nf i g ur a t io n is t h e sclk sig n al . the h o s t sys t em sho u ld c h a n g e t h e da ta line dir e c t io n wi th ref e r e n c e t o t h e ad7732 timin g s p ecif ic a t ion (s ee the b u s re l i nq uis h t i m e in t a b l e 2). the ad7732 ca nn ot o p era t e in t h e c o n t i n uo us r e ad m o de i n 2- wir e s e r i al in t e r f ace co nf igura t io n. a l l t h e dig i t a l i n t e r f ace i n p u ts a r e s c hmi t t- t r ig g e r e d; t h er efo r e , th e ad7732 in ter f ace f e a t ur es hig h er n o is e imm u ni ty an d can be e a sil y is ola t e d f r o m the h o st sys t em v i a o p t o co u p lers. f i gur e 13, f i gur e 14, a nd f i gur e 15 o u tlin e s o me o f th e p o s s i b le h o st de vice in te r f aces: s p i w i t h o u t usin g t h e cs sig n al (f igur e 13), a ds p in t e r f ace (f igur e 14), a n d a 2-wir e co nf igura t io n(f i gur e 15). sclk din dout cs rdy reset dgnd dv dd dv dd ad7732 sck mosi miso int 68hc11 ss f i gur e 1 3 . ad77 32 t o h o st de vi c e int e r f a c e , sp i sclk din dout cs rdy reset dv dd ad7732 sclk dt dr int tfs rfs adsp-2105 f i gur e 1 4 . ad77 32 t o h o st de vi c e int e r f a c e , dsp sclk din dout cs reset dgnd dv dd ad7732 p3.1/txd p3.0/rxd 8xc51 f i gu r e 1 5 . ad 77 32 t o h o st de vi c e i n t e r f a c e , 2 - w i r e co n f igu r a t io n
ad7732 res e t the ad7732 can b e r e s e t b y the res e t p i n o r b y wr i t in g a r e s e t s e q u en ce t o t h e ad7732 s e r i al in t e r f ace . the r e s e t s e q u en ce is n 0 + 32 1, whic h cou l d be t h e da t a seq u en ce 00h + ffh + ffh + ff h + ffh in a b y te-o r i en t e d in t e r f ace . the ad7732 als o f e a t ur es a p o w e r - o n r e s e t wi th a t r i p p o in t o f 2 v a nd go es to t h e d e f i ne d d e fa u l t st a t e a f ter po w e r - o n . i t is th e syst em desig n er s r e sp on si b i li ty t o p r e v en t an u n wan t e d wr i t e op era t io n t o th e ad7732. the u n wan t e d wr i t e op era t io n co u l d ha pp en w h e n a sp ur io us clo c k a p p e a r s on t h e scl k w h i l e th e cs p i n is lo w . i t s h o u l d b e n o t e d tha t on sys t em p o w e r - on, if th e ad7732 in ter f ace sig n als a r e f l o a tin g o r undef i n e d , t h e p a r t ca n b e inad ver t e n t ly co nf igur e d in t o a n u n k n o w n st a t e . this co u l d be e a sil y o v er co m e b y ini t ia tin g ei t h er a ha r d wa r e r e s e t ev e n t o r a 32 o n e s r e se t seq u en ce a s th e f i r s t s t ep i n t h e s y s t em co nf igura t io n. access the ad7732 registers a l l co mm uni c a t io n s t o t h e p a r t s t a r t w i t h a wr i t e o p era t io n t o t h e comm unic a t io n s r e g i s t er fol l o w e d b y ei t h er r e adin g o r wr i t i n g t h e addr es s e d r e g i st er . i n a si m u l t ane o us r e ad-wr i t e i n t e r f ace (such as s p i), wr i t e 0 t o th e ad7732 while r e adin g da t a . f i gur e 16 s h o w s th e ad7732 in ter f ace r e ad s e q u en c e f o r th e ad c st a t us r e g i s t er . din sclk cs dout write communications register read adc status register f i gur e 1 6 . ser i a l inter f a ce si gnal s regi st er s a c c e ss single conversion and reading data w h en t h e m o de r e g i s t er is b e ing wr i t t e n, t h e a d c s t a t us b y t e is cle a r e d an d t h e rd y pi n g o e s h i g h , r e g a rd l e s s of it s pre v i ou s s t a t e . w h e n t h e sin g le co n v ersio n co mmand is wr i t t e n t o t h e m o de r e g i s t er , t h e ad c s t a r ts t h e con v ersion o n t h e cha n ne l s e le c t e d b y t h e addr es s o f t h e m o de r e g i s t er . af t e r t h e co n v ersio n is com p let e d , t h e da t a r e g i s t er is u p da t e d , t h e m o de r e g i st er is cha n ge d t o id le m o de , t h e r e l e van t r d y b i t is s e t, a nd t h e rd y p i n go e s lo w . th e rd y b i t is r e s e t an d t h e rd y pi n re tu r n s h i g h w h e n t h e rel e v a n t ch an nel d a t a re g i ste r i s be in g r e a d . f i gur e 17 s h o w s t h e dig i t a l in t e r f ace sig n als exe c u t in g a si n g le co n v ersio n on c h a n n e l 0, wai t in g fo r t h e rd y p i n to g o l o w , an d re a d i n g t h e c h an nel 0 d a t a re g i ste r . din sclk cs dout write communications register write mode register rdy conversion time read data register 38h 40h 48h (00h) (00h) data data write communications register f i g u re 17. s e ri al int e r f ace s i g n a l ss i ng le conve r s i on co mm and and 1 6 -bit s d a t a r e ading rev. 0 | page 23 of 32
ad7732 dump mo de w h en t h e d u mp b i t in t h e mo de r e g i s t er is s e t t o 1, th e c h ann e l s t a t us r e g i s t er wil l be r e ad immedia t e l y b y a r e ad o f th e c h ann e l da t a r e g i s t er , r e ga r d les s o f w h et h e r t h e s t a t us o r t h e da t a r e g i s t e r has b e en addr ess e d t h r o ug h t h e co mm uni c a t ion s r e g i s t er . th e din p i n sh o u ld n o t b e h i g h w h i l e r e adin g 24 -b i t da t a i n d u m p m o de; o t h e r w is e , th e ad7732 wil l be r e s e t. f i gur e 18 s h o w s th e dig i t a l in t e r f ace sig n als exe c u t in g a sin g le co n v ersio n on cha n n e l 0, wai t in g f o r th e rd y p i n to g o l o w , a nd r e adi n g t h e c h a n n e l 0 st a t us r e g i ster a nd d a t a r e g i ster i n th e d u m p m o d e . continuo us conv ersion mode w h en t h e m o de r e g i s t er is being wr i t t e n, th e ad c s t a t us b y t e is cle a r e d an d t h e rd y pi n g o e s h i g h , r e g a rd l e s s of it s pre v i ou s st a t e. w h e n t h e co n t i n uo us co n v ersio n co mmand is wr i t ten to t h e m o de r e g i s t er , t h e a d c s t a r ts co n v ersio n on t h e cha n ne l s e le c t e d b y t h e addr es s o f t h e m o de r e g i s t er . a f t e r th e co n v er si o n i s co m p le t e , th e r e lev a n t ch a n n e l da ta r e g i ster an d channel st a t us r e g i ster a r e u p da te d , t h e r e l e van t rd y b i t in the ad c sta t us r e g i s t er is s e t, and t h e ad7732 co n t i n ues con v e r t i n g o n t h e n e xt ena b le d cha n ne l . th e p a r t w i l l c y c l e thr o ug h all ena b le d c h a n ne ls un til p u t in to a n o t h e r m o de o r r e s e t. th e c y cle p e r i o d wi l l b e t h e s u m o f al l ena b le d ch an nel s c o n v e r s i on t i me s , s e t b y t h e c o r r e s p o nd i n g ch a n nel co n v ersio n t i m e r e g i s t ers. the r d y b i t is r e s e t w h en t h e re le van t chann e l da t a r e g i s t er is be in g r e a d . th e be ha v i o r o f th e rd y p i n de p e n d s on t h e rd yf n b i t i n t h e i / o p o r t r e g i s t er . w h e n t h e rd yf n b i t is 0, th e rd y p i n go es lo w w h e n an y channel has unr e a d d a t a . w h e n t h e r d yf n b i t is s e t t o 1, t h e rd y p i n wil l o n l y g o lo w if al l e n abl e d ch an ne l s h a ve u n re a d d a t a . i f an a d c c o n v e r s i on re su lt h a s not b e e n re a d b e f o re a n e w ad c con v ersion is co m p le t e d , t h e ne w r e s u l t wi l l o v er wr i t e t h e p r e v i o u s o n e . th e r e l e van t r d y b i t g o es lo w and t h e rd y pi n g o es hig h f o r a t leas t 163 m c lk c y c l es (~26.5 s ), in dica t i n g w h en t h e da t a r e g i s t er is u p da t e d an d t h e p r e v i o us co n v ersio n da ta i s los t . i f th e da ta r e g i st er is bein g r e ad as a n ad c con v ersio n c o m p l e t e s , th e d a t a r e gi s t e r w i ll n o t b e u p d a t e d w i th th e n e w r e su l t (to a v o i d d a t a co r r u p t i o n ) a nd t h e ne w c o n v ersio n da ta i s los t . f i gur e 19 s h o w s t h e dig i t a l in t e r f ace sig n al s s e quen ce fo r t h e co n t in uo us co n v ersio n m o de wi th chann e ls 0 and 1 ena b le d a nd t h e r d yf n b i t s e t t o 0. th e rd y p i n go es lo w and t h e d a t a re g i ste r i s re a d af te r e a ch c o n v e r s i on . f i g u re 2 0 show s a s i m i l a r s e q u e n ce b u t w i t h t h e rd yfn b i t s e t t o 1. th e rd y pi n g o e s l o w and a l l d a t a re g i ste r s are re a d af te r a l l c o n v e r s i ons are co m p let e d . f i gu r e 21 s h o w s t h e rd y p i n w h en n o da t a a r e r e ad f r o m th e ad77 32. din sclk cs dout write communications register write mode register rdy conversion time read data register read channel status 38h 48h 48h write communications register (00h) (00h) (00h) status data data f i g u re 18. s e ri al int e r f ace s i g n a l ss i ng le conve r s i on co mm and , 1 6 -bit s d a t a r e ad ing , d u mp m o de serial interface start continuous conversion rdy ch0 conversion read data ch1 ch1 conversion ch0 conversion read data ch0 ch1 conversion read data ch0 ch0 conversion read data ch1 f i g u re 19. cont inu o us co nvers i on, ch 0 a n d ch 1, r d yfn = 0 rev. 0 | page 24 of 32
ad7732 serial interface start continuous conversion rdy ch0 conversion read data ch1 ch1 conversion ch0 conversion read data ch0 ch1 conversion read data ch0 ch0 conversion read data ch1 f i g u re 20. cont inu o us co nvers i on, ch 0 a n d ch 1, r d yfn = 1 serial interface start continuous conversion rdy ch0 conversion ch1 conversion ch0 conversion ch1 conversion ch0 conversion f i g u re 21. cont inu o us co nvers i on, ch 0 a n d ch 1, no d a t a r e ad din 48h 00h data 00h data 00h status read ch0 data read ch0 status 48h write comm. register sclk cs dout write comm. register write mode register rdy 38h 00h data 00h data 00h status read ch1 data read ch1 status conversion on ch0 complete conversion on ch1 complete f i g u re 22. cont inu o us co nvers i on, ch 0 a n d ch 1, cont inuous r e ad continuous read (continuous conversion) mode w h en t h e c o n t rd b i t i n t h e mo de r e g i s t er is s e t, t h e f i rs t wr i t e o f 48h t o t h e comm uni c a t io n s reg i s t er s t a r ts t h e co n t i n uo us r e ad m o de . a s sh o w n in f i gur e 22, s u bs eq uen t acces s es t o t h e p a r t s e q u en t i al ly r e ad t h e chann e l s t a t us and da t a r e g i s t ers o f t h e l a st com p lete d con v ersio n wi t h o u t an y f u r t h e r co nf igur a t i o n o f t h e co mm uni c a t ion s r e g i s t er b e i n g r e q u ir e d . n o t e t h a t t h e con t i n uo us co n v e r sio n b i t in t h e m o de r e g i s t er s h o u ld b e s e t w h e n en t e r i n g t h e co n t i n uo us r e ad m o de . n o t e tha t t h e con t in uo us r e ad m o de is a d u m p m o de r e adin g o f t h e ch a n nel s t atu s and d a t a re g i ste r s re g a rd l e ss of t h e d u m p bit val u e . u s e t h e cha n n e l b i ts in t h e chann e l s t a t us r e g i s t er t o ch e c k/r e cog n i z e t h a t chan n e l d a t a is ac t u a l ly b e in g sh if t e d o u t. n o t e tha t t h e las t co m p let e d con v ersio n r e s u l t is bein g r e ad . ther efo r e t h e r d yfn b i t i n t h e i/o p o r t r e g i s t e r s h o u ld b e 0 and re adi n g t h e re su l t shou l d a l wa y s st ar t b e fore t h e ne x t co n v ersio n is com p let e d . the ad7732 wi l l s t a y in co n t in uo us r e ad m o de as lo n g as t h e d i n p i n is lo w w h i l e t h e cs p i n is lo w ; t h er efo r e , wr i t e 0 t o t h e ad7732 while r e adin g in con t in uo us r e ad m o de . t o exi t co n t in uo us r e ad m o de , ta k e t h e d i n p i n hig h f o r a t leas t 100 n s a f t e r a r e ad is c o m p let e . ( w r i t e 80h t o the ad7 732 t o exi t co n t in uo us r e adin g.) t a k i n g t h e di n p i n hi g h do e s no t cha n ge t h e c o n t r d b i t i n t h e m o de r e g i s t er . th er efo r e , t h e n e xt wr i t e o f 48h s t a r ts t h e co n t in uo us r e ad m o de a g a i n. t o co m p let e l y st op th e con t in uo us r e ad m o de , wr i t e t o t h e mo de reg i s t er t o cle a r t h e c o n t rd b i t. rev. 0 | page 25 of 32
ad7732 circuit description the ad7732 is a sig m a-de l t a ad c tha t is in t e nded f o r th e me a s u r e m e n t of w i d e dy n a m i c r a nge, l o w f r e q ue nc y s i g n a l s i n ind u st r i a l p r o c e s s c o n t rol, inst r u me n t a t ion, and plc s y ste m s . i t co n t ain s thin f i lm r e sis t o r dividers, a m u l t i p lexer , a n in p u t b u f f er , a sig m a- del t a (o r cha r ge b a lan c i n g) ad c, a dig i t a l f i l t er , a clo c k os ci l l a t o r , a dig i t a l i / o p o r t , a n d a s e r i a l co mm uni c a t io ns in t e r f ace. analog fr ont end the ad7732 f e a t ur es tw o f u l l y dif f er en tial a n al og in p u ts. the o n -c hi p thin f i lm r e sis t o r dividers al lo w 10 v , 5 v , 0 v t o +10 v , a nd 0 v to +5 v in p u t sig n a l s to b e conne c t e d dir e c t ly to t h e an a l o g i n put pi ns . the r e sis t o r div i der in p u t s t a g e is fol l o w e d b y t h e m u l t i p lexer a nd t h en b y a w i de b a nd w i d t h, fast s e t t lin g t i m e dif f er en t i a l in p u t b u f f er ca p a b l e o f dr i v i n g t h e d y na mic lo ad o f a hig h s p e e d sig m a-d e l t a m o d u l a t o r . i n n o r m a l cir c ui t co nf igur a t ion, t h e bi as pin s ar e co nne c t e d to t h e 2.5 v (r efer en ce) v o l t a g e s o u r ce . this en s u r e s t h a t t h e dif f er en t i al sig n al s e en b y t h e i n t e r n al in p u t b u f f er is wi t h i n i t s a b s o l u te /co m mo n- m o d e ra n g e o f a g nd + 200 mv to av dd C 300 mv . the ad7732 ai n dif f er en t i al vol t a g e sh o u ld b e wi thin the sp e c if ie d n o min a l (u p t o 10 v) in p u t ran g e , o t h e r w is e t h e p e r f or m a nc e on ch an nel m i g h t d e g r a d e ( s e e t h e a n a l o g i n put s e x te nd e d v o lt a g e r a nge sect i o n ) . the ad7732 inl p e r f o r ma n c e va r i es wi t h t h e ain co mm on- m o de v o l t a g e (f igur e 9). th e dif f er en t i al a n alog in p u t v o l t a g e o f 10 v wi t h a comm on- m o d e vol t a g e o f 0 v me a n s t h a t t h e ai n dif f er en t i al v o l t a g e is ce n t er e d a r o u n d a g nd a nd b o t h ain( +) a nd ai n(C) c h an g e wi thin 5 v r e s p ec t t o a g nd . th e ad7732 inl als o va r i es wi t h t h e m c l k f r eq uen c y (f igur e 7). i f t h e bi a s pin s a r e in n o r m a l c o nf igura t io n, t h e ai n p i n a b s o l u t e v o l t a g e u p t o 16.5 v do es n o t deg r ade th e ad jacen t ch an nel s p e r f or m a n c e. a n a i n ab s o lute volt age ove r 1 6 . 5 v r e su l t s in c u r r en t f l o w in g t h r o ug h t h e in t e r n a l p r o t e c t i o n dio d es lo c a te d b e hi n d t h e t h in f i lm r e sis t o r s; t h e ad jac e n t cha n n e l ca n b e a f fe c t e d . by co nf igur in g t h e bi as and r a to r d p i n s dif f er en t l y , t h e p a r t wi l l w o rk w i t h hig h er ain a b s o l u t e v o l t a g es as lo n g as t h e in t e r n al v o l t a g e s e en b y t h e m u l t i p lexer a nd in p u t b u f f er is wi thin 200 mv t o a v dd C 300 mv . a b s o l u t e volt age for t h e a i n, bi as , a n d r a to r d pi ns m u st ne ve r exce e d t h e val u es s p e c if ie d i n t h e a b s o l u t e m a xim u m r a t i n g s. n o t e t h a t t h e o v r b i t i n t h e cha nne l st a t us r e g i s t er is g e n e ra te d dig i t a l l y f r o m t h e con v ersion r e su l t an d i n dic a tes t h e sig m a- d e l t a m o d u la t o r (n o m inal) o v erra n g e . th e o v r b i t d o es not indic a te exce e d i n g t h e ai n p i n a b s o l u te /co m mo n- m o d e vol t age l i mi t s . f i gur e 23 s h o w s th e ad7732 a n alog in p u t in t e r n al s t r u c t ur e . bias ain 1r 7r 108.5k ? 15.5k ? av dd mux protection diodes agnd 2.1875v 1.25v 2.5v 10v buffer f i gure 23. si mpl i fi e d a n al og input i n te rna l stru c t ur e rev. 0 | page 26 of 32
ad7732 rev. 0 | page 27 of 32 analog in puts extended vol t age r a ng e the ad7732 o u t p u t da t a co de sp a n co r r es p o n d s t o th e n o mina l in p u t v o l t a g e ra n g e . th e ad c i s f u n c t i o n al o u t s ide t h e n o mina l in p u t v o l t a g e ra n g e , b u t t h e p e r f o r ma n c e mig h t deg r ade . th e sig m a-de l t a m o d u l a t o r was desig n e d t o f u l l y co v e r a 11.6 v dif f er en t i al in put v o l t a g e; o u tsi d e t h is ra n g e , t h e p e r f o r ma n c e mig h t deg r ade m o r e ra p i dl y . th e ad jace n t channe ls a r e n o t af fe c t e d b y up t o 1 6 . 5 v ab s o lute an a l o g i n put volt age (f igur e 8). w h en t h e c l a m p b i t in t h e mo de r e g i s t er is s e t t o 1, t h e cha n n e l da t a r e g i s t er wi l l b e di g i t a l l y cla m p e d t o ei t h er al l 0s o r al l 1s w h en t h e a n alog in p u t v o l t a g e g o es o u tside t h e n o minal i n put vol t ag e r a nge. a s sh o w n in t a b l e 16 an d t a b l e 17, wh en cl amp = 0, th e da t a r e f l e c ts t h e a n al og in p u t v o l t a g e o u tside t h e n o minal v o l t a g e ra n g e . i n th i s case , th e s i gn a n d o v r b i t s i n t h e c h a n n e l s t a t us r e g i s t er sh o u ld b e con s ider e d al o n g w i t h t h e da t a r e g i s t er va l u e to de co de t h e a c t u a l con v ersion r e su l t . n o t e t h a t t h e o v r b i t i n t h e cha nne l st a t us r e g i s t er is g e n e ra te d dig i t a l l y f r o m t h e con v ersion r e su l t an d i n dic a tes t h e sig m a- d e l t a m o d u la t o r (n o m inal) o v erra n g e . th e o v r b i t d o es not i n d i ca t e e x ceed in g th e a i n p i n s a b so l u t e v o l t a g e l i m i t s . table 16. ext e nde d input voltage range, nominal volt age range 10 v, 16 bits, clamp = 0 input (v) data (hex) sign ovr 1 1 . 6 0 0 3 9 1 4 7 b 0 1 1 0 . 0 0 0 6 1 0 0 0 1 0 1 1 0 . 0 0 0 3 1 0 0 0 0 0 1 1 0 . 0 0 0 0 0 f f f f 0 0 0 . 0 0 0 3 1 8 0 0 1 0 0 0 . 0 0 0 0 0 8 0 0 0 0 0 C 0 . 0 0 0 3 1 7 f f f 1 0 C 1 0 . 0 0 0 0 0 0 0 0 0 1 0 C 1 0 . 0 0 0 3 1 f f f f 1 1 C 1 0 . 0 0 0 6 1 f f f e 1 1 C 1 1 . 6 0 0 4 0 e b 8 5 1 1 table 17. ext e nde d input voltage ran g e, nominal voltage ran g e 0 v to + 1 0 v , 16 bits, cla m p = 0 input (v) data (hex) sign ovr 1 1 . 6 0 0 0 6 2 8 f 5 0 1 1 0 . 0 0 0 3 1 0 0 0 1 0 1 1 0 . 0 0 0 1 5 0 0 0 0 0 1 1 0 . 0 0 0 0 0 f f f f 0 0 0 . 0 0 0 1 5 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 0 0 0 C 0 . 0 0 0 1 5 0 0 0 0 1 1 chopping w i t h ch o p p i n g ena b le d , t h e m u l t i p lexer r e p e a t e d l y r e v e rs es t h e ad c i n p u ts. e v er y o u t p u t d a t a r e su l t is t h e n ca lc u l a t e d as an a v era g e o f t w o co n v ersio n s, t h e f i rs t w i t h t h e p o si t i v e and t h e s e con d w i t h t h e n e g a t i ve o f fs et t e r m i n cl ude d . this ef fe c t i v e l y r e m o v e s a n y o f fs et er r o r o f t h e in p u t b u f f er a n d sig m a-de l t a mo d u l a tor . h o we ver , chop ping is a p pl ie d on ly b e hi nd t h e i n p u t r e s i stor divider s t a g e; t h er efo r e , ch o p p i ng do es n o t e l i m i n a t e t h e o f fs et e r ror and d r i f t s c a u s e d by t h e re s i stor s . f i g u re 2 4 show s t h e ch an nel s i g n a l c h ai n w i t h c h oppi ng e n a b l e d. + - di g i t a l in t e r f a c e ch o p cho p f mc l k /2 f mc l k /2 b u ffe r mu l t i p l exer di g i t a l fi lt e r sc a l i n g ar i t hm e t i c ( cal i brat i o ns ) o u tp u t d a ta a t t h e sel ec t e d dat a rat e ai n( + ) ai n ( ? ) bi as ( + ) bi as ( ? ) ? ? m o dul at o r f i gure 24. channe l signal ch ain d i agr a m with chop ping enabled
ad7732 multiplexer, conver sion, and data output timing the sp e c if ie d c o n v ersio n t i m e in cl ude s o n e o r tw o s e t t lin g and s a m p ling p e r i o d s a nd a s c a l i n g t i me. w i t h ch o p p i n g ena b le d (f igur e 25), a co n v ersion c y cle s t a r ts wi t h a s e t t lin g tim e o f 43 m c lk c y c l es o r 44 m c lk c y c l es (~7 s wi th a 6 . 144 mh z m c l k ) t o al lo w th e cir c ui ts f o l l o w in g th e m u l t i p lexer t o s e t t le . th e sig m a-de l t a m o d u l a t o r th en s a m p les t h e a n alog sig n als a n d t h e dig i t a l f i l t er p r o c es s e s t h e dig i t a l da t a st r e a m . t h e s a m p lin g t i m e de p e nds o n f w , i . e., o n t h e cha n nel co n v ersio n t i m e r e g i s t er co n t en t s . af t e r a n o t h e r s e t t ling o f 42 m c lk c y c l es (~6.8 s), th e s a m p lin g t i m e is r e p e a t ed wi th a r e v e r s ed (ch o p p ed ) a n al og i n p u t s i gn al . th e n , d u ri n g th e s c alin g t i m e o f 163 m c lk c y c l es (~26.5 s), th e tw o r e s u l t s f r o m t h e dig i t a l f i l t er a r e a v era g e d , s c ale d usin g t h e calib r a t ion r e g i sters, a nd w r i t te n in to t h e cha n n e l d a t a r e g i ster . w i t h ch o p p i n g dis a b l e d (f igur e 26), t h er e is o n ly o n e s a m p lin g time p r eceded b y a s e t t lin g tim e o f 43 m c lk c y c l es o r 44 m c lk c y c l e s a nd f o l l o w ed b y a s c alin g time o f 163 m c lk c y c l es. the rd y p i n g o es hig h d u r i n g t h e s c alin g tim e , r e ga rdles s o f i t s p r evi o u s s t a t e . t h e r e l eva n t rd y b i t i s se t in t h e a d c s t a t us r e g i s t er an d in t h e chann e l s t a t us r e g i s t er , a n d t h e rd y pi n g o e s lo w w h e n t h e cha n n e l d a t a r e g i ster is u p d a te d and t h e cha n nel co n v ersio n c y cle is f i nish e d . i f i n co n t in uo us con v ersio n m o de , t h e p a r t wi l l a u to ma t i c a l l y co n t i n ue wi t h a con v ersio n c y cle o n t h e n e xt enab le d cha n ne l . n o te t h a t e v er y cha n n e l ca n b e co nf igur e d i n de p e nden t ly fo r co n v ersio n t i m e a nd ch o p p i n g m o de . th e o v eral l c y cle a n d ef fe c t i v e p e r cha nnel d a t a r a tes dep e n d on a l l e n a b le d chan nel s e t t i n g s . sigma- del t a ad c the ad7732 cor e co n s is ts o f a c h a r g e balan c ing sig m a-de l t a m o d u l a to r and a dig i t a l f i l t er . t h e a r ch i t e c t u r e i s o p t i mi ze d fo r fas t , f u l l y s e t t le d co n v ersio n . this al lo ws f o r fas t c h a n n e l-t o - cha n n e l s w i t chi n g w h ile ma in t a inin g i n h e r e n t l y exce l l en t lin e a r i t y , hig h r e s o l u tio n , and lo w n o is e . ? channel 1 scaling time sampling time + channel 1 sampling time settling time multiplexer ? channel 0 rdy settling time conversion time f i g u re 25. m u lt ip le x e r a n d co nvers i on ti mi ng c ont i nu ous co nvers i on on s e ver a l cha nne ls wit h ch op p i ng e n a b led scaling time channel 1 sampling time multiplexer channel 0 rdy settling time conversion time f i g u re 26. m u lt ip le x e r a n d co nvers i on ti mi ng c ont i nu ous co nvers i on on s e ver a l cha nne ls wit h ch op p i ng d i s a bl ed rev. 0 | page 28 of 32
ad7732 frequency response t h e si gm a- d e l t a m o d u la t o r r u n s a t ? th e m c lk f r eq uen c y , w h ich is ef fe c t i v e l y t h e s a m p li ng f r e q uen c y . ther efo r e , t h e n y q u i s t fr e q u e n c y i s ? t h e m c l k fr e q u e n c y . t h e d i g i t a l fi l t e r , in ass o c i a t ion w i t h t h e m o d u l a to r , fe a t ur es t h e f r e q uen c y re sp ons e of a f i r s t ord e r l o w - p a s s f i lte r . t h e C 3 d b p o i n t i s cl o s e t o th e f r eq uen c y o f 1/c h a nne l c o n v ersio n t i m e . the r o l l -o f f is C 20 db/dec u p t o th e n y q u is t f r e q uen c y . i f c h op p i n g is enab led , t h e i n p u t sig n al is r e s a m p le d b y ch o p ping. th er efo r e , t h e o v eral l f r e q uen c y r e s p o n s e fe a t ur es n o tch e s clos e t o t h e f r e q uen c y o f 1 / ch an ne l c o n v e r s i on t i me. t h e top e n vel op e i s ag ai n t h e a d c re sp ons e of C 2 0 d b / d e c . t h e t y pi c a l f r e q u e nc y re sp ons e pl ot s are g i ve n i n f i g u re 2 7 a nd f i gur e 28. the p l o t s a r e n o r m alize d t o 1/cha n n e l co n v ersio n t i m e . normalized input frequency (input frequency conversion time) gain ? db ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 0.1 1.0 10.0 chop = 1 f i gure 27. t y pic a l a d c f r equenc y r e sp onse , chop ping en abled normalized input frequency (input frequency conversion time) gain ? db ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 1.0 0.1 10.0 100.0 1000.0 chop = 0 f i gure 28. t y pic a l a d c f r equenc y r e sp onse , chop ping d i s a bled voltag e r e fer e nc e i n puts the ad7732 has a dif f er en t i al ref e r e n c e in p u t, ref in(+) a nd ref in(C). th e co mm o n - m o d e ra n g e fo r t h es e in p u ts is f r o m ag n d t o a v dd . the n o mina l di f f er en t i al r e fer e n c e v o l t a g e fo r sp e c if ie d o p er a t io n is 2.5 v . b o t h r e fer e n c e i n pu ts fe a t ur e d y na mic lo ad . th er efo r e , t h e r e fer e n c e in pu ts sho u ld b e co nne c t e d to a l o w im p e dance r e fer e n c e vol t a g e s o ur ce. e x t e r n a l r e sist a n ce /c a p aci t an ce co m b in a t io ns ma y r e su l t i n ga in er r o rs o n t h e p a r t . the o u t p u t n o is e p e r f o r ma n c e o u t l in e d i n t a b l e 4 t h r o ug h t a bl e 9 i s for an an a l o g i n put of 0 v an d i s u n af fe c t e d b y noi s e o n t h e r e fer e n c e. t o ob t a in t h e s a me n o i s e p e r f o r ma n c e as s h own i n t h e n o is e t a b l es o v er t h e f u l l i n p u t rang e r e q u ir es a lo w n o is e r e f e r e n c e s o ur ce f o r th e ad7732. i f t h e r e f e r e nce n o is e in t h e b a nd w i d t h o f in ter e st is excessi v e , i t wi l l d e g r ade t h e p e r f o r ma n c e o f t h e ad773 2. recomm en de d r e f e r e n c e v o l t a g e s o ur ces f o r th e ad7732 in c l ude t h e ad780, ad r421, ref43, a n d ref1 92. n o t e tha t in a typ i cal conn e c t i o n , t h e v o l t a g e refer e n c e m u s t b e ca p a b l e o f s i n k i n g c u r r e n t f l ow i n g out of t h e bi as pi ns t h rou g h t h e in t e r n a l r e sist o r s if a p o si t i v e v o l t a g e is a p plie d to t h e a n a l og in p u t. th e ad7 80 m e e t s t h is r e q u ir em e n t. i f t h e v o l t a g e r e fer e n c e us e d i n a n a p pli c a t io n is n o t ca p a b l e of sin k in g c u r r en t, a n ext e r n al r e sis t o r (5 k?) s h o u l d b e c o nn e c t e d in pa r a ll e l t o th e re fi n p i n s . ref e renc e detec t the ad7732 inc l udes o n -c hi p cir c ui tr y t o det e c t if th e p a r t has a valid r e fer e n c e fo r co n v ersio n s. i f t h e v o l t a g e b e tw e e n t h e refin(+) a nd refin(C) p i n s g o es b e lo w t h e n o ref t r ig g e r v o l t a g e (0.5 v typ) a n d t h e ad7732 is p e r f o r m i n g a con v ersion, t h e n o ref b i t in t h e cha n ne l s t a t us r e g i st er is s e t. rev. 0 | page 29 of 32
ad7732 rev. 0 | page 30 of 32 i/o port the ad7732 p0 pin can be used as a general-purpose digital i/o pin. the p1 pin ( sync /p1) can be used as a general- purpose digital i/o pin or to synchronize the ad7732 with other devices in the system. when the sync bit in the i/o port register is set and the sync pin is low, the ad7732 does not process any conversion. if it is put into single conversion mode, continuous conversion mode, or any calibration mode, the ad7732 waits until the sync pin goes high and then starts operation. this allows conversion to start from a known point in time, i.e., the rising edge of the sync pin. the digital p0 and p1 voltage is referenced to the analog supplies. when configured as inputs, the pins should be tied high or low. calibration the ad7732 provides zero-scale self-calibration and zero- and full-scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise. after each conversion, the adc conversion result is scaled using the adc calibration registers and the relevant channel calibration registers before being written to the data register. for unipolar ranges: data = ((adc result ? adc zs cal. reg.) adc fs reg./200000h ? ch. zs cal. reg.) ch. fs cal. reg./200000h for bipolar ranges: data = ((adc result ? adc zs cal. reg.) adc fs reg./400000h + 800000h ? ch. zs cal. reg.) ch. fs cal. reg./200000h where the adc result is in the range of 0 to ffffffh. note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. it is strongly recommended that the user not change the adc full- scale register. to start any calibration, write the relevant mode bits to the ad7732 mode register. after the calibration is complete, the contents of the corresponding calibration registers are updated, all rdy bits in the adc status register are set, the rdy pin goes low, and the ad7732 reverts to idle mode. the calibration duration is the same as the conversion time configured on the selected channel. a longer conversion time gives less noise and yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration. adc zero-scale self-calibration the adc zero-scale self-calibration can reduce the offset error in the chopping disabled mode. if repeated after a temperature change, it can also reduce the offset drift error in the chopping disabled mode. the zero-scale self-calibration is performed on internally shorted adc inputs. the negative analog input terminal on the selected channel is used to set the adc zero-scale calibration common mode. therefore, either the negative terminal of the selected differential pair or the aincom on the single-ended channel configuration should be driven to a proper common- mode voltage. it is strongly recommended that the adc zero-scale calibration register should only be updated as part of a zero-scale self- calibration. per channel system calibration if the per channel system calibrations are used, these should be initiated in the following order: a channel zero-scale system calibration, followed by a channel full-scale system calibration. the system calibration is affected by the adc zero-scale and full-scale calibration registers. therefore, if both self-calibration and system calibration are used in the system, an adc full-scale self-calibration should be performed first, followed by a system calibration cycle. while executing a system calibration, the fully settled system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs. the per channel calibration registers can be read, stored, or modified and written back to the ad7732. note that when writing the calibration registers the ad7732 must be in idle mode. note that outside the specified calibration range, calibration is possible but the performance may degrade (see the system calibration section in table 1).
ad7732 rev. 0 | page 31 of 32 + 10 f 0.1 f + 10 f 0.1 f analog inputs r=15.5k ? r clock generator mclkin mclkout 33pf 33pf 6.144mhz ain0(+) bias0(+) ra rb bias0(?) rc rd 10v differential voltage 10v differential voltage (max 16.5v absolute voltage to agnd) 11.5v common- mode voltage 7r=108.5k ? mux r 7r 7r 24-bit - ? adc buffer dv dd ain0(?) ain1(+) bias1(+) refin( ? ) refin(+) agnd 10 f + 0.01 f + 10 f ad780 vout +vin temp +2.5v ad7732 r 7r serial interface and control logic sclk din dout cs rdy reset dgnd host system ain1(?) bias1(?) av dd av dd dv dd dv dd av dd f i g u re 29. t y pic a l conne c t io ns f o r t h e a d 77 32 a p pl ic at i o n high co mmon- m od e vol t age applic atio n u s in g addi tio n a l thin f i lm r e sis t o r s o n ai n0 and a n ext e r n al op era t io nal am p l if ier wi t h a 15 v p o w e r s u p p l y , th e ad7732 ain0 c an ea s i l y be co n f i g ur ed t o a cce p t hi gh co mm o n -m od e v o l t a g es . +15v ?15v + 10 f 0.1 f + 10 f 0.1 f analog inputs r=15.5k ? 2r 2r 2r 2r clock generator mclkin mclkout 33pf 33pf 6.144mhz ain0(+) bias0(+) ra rb bias0(? ) rc rd 10v differential voltage ( 42v absolute max voltag e to agnd) 37v common- mode voltage 7r=108.5k ? mux 7r 24-bit - ? adc buffer dv dd ain0(? ) refin(?) refin(+) agnd 10 f + 0.01 f + 10 f ad780 vout +vin temp +2.5v ad7732 serial interface and control logic sclk din dout cs rdy reset dgnd host system av dd av dd dv dd dv dd av dd f i g u re 30. h i g h co mm on-m ode v o lt a g e a p pl ic at io n
ad7732 outline dimensions 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10 f i g u re 31. 2 8 -l ead this sh rink sm al l o u t lin e p a ck a g e [ t ssop ] (r u-2 8 ) d im e n s i o n s sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. table 18. ordering guide ad77 32 prod ucts temperature p a ckage package descri ption package outlin e AD7732BRU C40c to +105c tssop-28 ru-28 ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . prin ted in th e u.s . a. c03070-0-2/03(0) rev. 0 | page 32 of 32

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